RDC Verification

FishTail’s RDC verification solution verifies that the path through an asynchronous reset pin on a flop is false. We strongly recommend RTL input for RDC Verification.

RDC Verification Features

Verification of Reset Domain Crossing

Our RDC verification solution verifies that if the async. reset pin on a flop is asserted, and the async. reset pin on the flop that it drives is not asserted then the path through the async. reset pin is false. This is necessary to ensure that STA does not need to time the path through the async. reset pin.

Assertions for failing RDC Checks

If an RDC check fails formal verification the tool generates SVA that captures the condition that must hold for the RDC check to pass. This assertion can be verified using RTL simulation.

RDC
Verification

What Makes us Different

All we require for RDC Verification is the RTL and SDC constraints for a design. No further information is required. If an RDC check fails formal proof, engineers do not need to debug the formal failures. Instead they take the SVA generated by the tool into RTL simulation and only debug those assertions that fail.

SDC Verification Solutions