FishTail’s RDC verification solution verifies that the path through an asynchronous reset pin on a flop is false. We strongly recommend RTL input for RDC Verification.
RDC Verification Features
RDC
Verification
What Makes us Different
All we require for RDC Verification is the RTL and SDC constraints for a design. No further information is required. If an RDC check fails formal proof, engineers do not need to debug the formal failures. Instead they take the SVA generated by the tool into RTL simulation and only debug those assertions that fail.