FishTail’s glitch verification solution establishes if asynchronous resets, clock pins and timing-exceptions are safe from glitches. We strongly recommend performing glitch verification with RTL input but support netlist input as well.
Glitch Verification Features
Glitch
Verification
What Makes us Different
The dominant approach to glitch verification in the industry today relies on gate-level simulation. This approach is woefully inadequate because it happens late in the design flow, gate-level simulation coverage is poor and simulating the design with specific delay values in the hope that it will throw up a glitch is naïve. FishTail’s solution to the problem requires as input collateral that is readily available (RTL and SDC) and establishes if a design is safe from glitches for any and all circuit delay. Most importantly, this approach leverages RTL simulation – the tool formally proves what it can and generates assertions for formal failures. So, RTL designers are not required to constrain a formal tool, or learn the debug environment that accompanies a formal tool. Instead, they simply review simulation assertion failures using techniques they are already familiar with.