FishTail’s glitch verification solution establishes if asynchronous resets, clock pins and timing-exceptions are safe from glitches. We strongly recommend performing glitch verification with RTL input but support netlist input as well.

Glitch Verification Features

Verification of Asynchronous Resets

We verify if any asynchronous reset on the design can glitch at its assertion level. We catch bugs where the reset logic on a design allows a glitch to be generated and then propagate to an asynchronous reset pin on a register.

Verification of Clock Pins

We verify if any clock pin on a register can glitch. We catch bugs where designers do not use glitch-free muxes and ICGs in the clock-generation logic for a design and so open themselves to silicon risk.

Verification of Timing Exceptions

We ensure that no timing exception allows a glitch to propagate along a path in a way that breaks the specified false or multi-cycle behavior. We catch bugs where a multi-cycle path that appears correct in cycle accurate RTL simulation, is actually a source of silicon risk because a single-cycle glitch can propagate along the path.

Glitch
Verification

What Makes us Different

The dominant approach to glitch verification in the industry today relies on gate-level simulation. This approach is woefully inadequate because it happens late in the design flow, gate-level simulation coverage is poor and simulating the design with specific delay values in the hope that it will throw up a glitch is naïve. FishTail’s solution to the problem requires as input collateral that is readily available (RTL and SDC) and establishes if a design is safe from glitches for any and all circuit delay. Most importantly, this approach leverages RTL simulation – the tool formally proves what it can and generates assertions for formal failures. So, RTL designers are not required to constrain a formal tool, or learn the debug environment that accompanies a formal tool. Instead, they simply review simulation assertion failures using techniques they are already familiar with.

SDC Verification Solutions

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RTL Glitch Verification

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