FishTail’s generated –clock verification solution establishes if the waveform specified for a generated clock (period, pulse-width) is supported by the logic on the design. We also verify if the alignment between generated clocks is correctly specified. Our generated-clock verification solution works off either RTL or netlist input and is routinely used as part of the signoff criteria for SoCs and IPs.

Generated-Clock Verification Features

Verification of Generated-Clock Waveform

We formally verify if the waveform specified for a generated clock is supported by the logic on the design and ensure that the period, high and low pulse widths are correctly specified. We catch mistakes such as the specification of an incorrect -divide_by value for a generated clock, or the inappropriate used of –divide_by when the duty cycle of a generated clock is not 50%.

Verification of Generated-Clock Alignment

We formally verify that the alignment between generated clocks derived from a common master clock is correctly specified. We also verify that the waveform specified on a generated clock definition pin is aligned with the waveform on the clock pins driven by the generated clock. By flagging generated clock alignment issues we identify situations where STA incorrectly assumes that more time is available to meet timing on paths between generated clocks, than what the logic actually supports.

Verification of
Generated-Clock Waveform

Verification of
Generated-Clock Alignment

What Makes us Different

An incorrect generated clock specification can easily result in silicon failure. Our generated-clock verification solution goes above and beyond the simple checks performed by STA and other tools to ensure that all aspects of a generated clock specification are consistent with the logic on the design. If a generated clock fails formal verification an engineer has the option to either review a failure stimulus and provide additional input to the tool (the way configuration registers are programmed, for example) or take SVA generated by the tool into simulation and confirm using ABV that the generated clocks are correctly specified. Closing on generated-clock failures is fast, not noisy and can be easily accomplished for all designs regardless of their complexity.

SDC Verification Solutions

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Constraint Verification

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Constraint Verification

Solution

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Constraint Verification

Solution

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