FishTail’s generated –clock verification solution establishes if the waveform specified for a generated clock (period, pulse-width) is supported by the logic on the design. We also verify if the alignment between generated clocks is correctly specified. Our generated-clock verification solution works off either RTL or netlist input and is routinely used as part of the signoff criteria for SoCs and IPs.
Generated-Clock Verification Features
Verification of
Generated-Clock Waveform
Verification of
Generated-Clock Alignment
What Makes us Different
An incorrect generated clock specification can easily result in silicon failure. Our generated-clock verification solution goes above and beyond the simple checks performed by STA and other tools to ensure that all aspects of a generated clock specification are consistent with the logic on the design. If a generated clock fails formal verification an engineer has the option to either review a failure stimulus and provide additional input to the tool (the way configuration registers are programmed, for example) or take SVA generated by the tool into simulation and confirm using ABV that the generated clocks are correctly specified. Closing on generated-clock failures is fast, not noisy and can be easily accomplished for all designs regardless of their complexity.