FishTail’s formal constraint lint works off netlist or RTL input with the constraints specified in either SDC or TCL format. It has been applied to designs with more than 100M cell instances and with more than thousands of clocks.

Constraint Lint Verification Features

FishTail’s formal constraint lint solution allows engineers to get feedback on the following aspects of their SDC constraints:

Clock Definitions

Are they complete, are clocks created on hierarchical pins

Generated Clock Definitions

Are they complete, are edges correctly specified, is there a path from master to generated clock

Clock Propagation

Is clock propagation stopped by the logic on the design, does a clock have reconvergent paths

Clock Crossings

Are clock crossings correctly constrained using false paths, clock groups

Case Analysis

Do case analysis values conflict with each other

Exception Issues

Do setup MCPs have accompanying hold MCPs, are there exceptions specified with a very broad scope, do exceptions overlap

Input Output Delay

Are input/output delays complete

SDC Syntax

Do constraints refer to objects that do not exist, or apply to objects that they should not, or are written

SDC Style Check

Are constraints written using best known methods, avoiding common pitfalls

Case Analysis
Verification

Clock Propagation
False Paths

Logically Exclusive
Clock Groups

What Makes us Different

FishTail’s formal constraint lint is not noisy. Subtle issues are reported. Formal technology is used to ensure that the warnings are legitimate and require review. Our primary focus is not on tool runtime but on reducing designer review and on reporting bugs that other tools do not catch. A powerful debug environment allows engineers to quickly rootcause issues.

SDC Verification Solutions

Download Documents

Constraint Verification

Demo

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Constraint Verification

White paper

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Constraint Verification

Presentation

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Formal Lint Issues

White paper

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