Formal Constraint Lint

Are they complete, are clocks created on hierarchical pins

Are they complete, are edges correctly specified, is there a path from master to generated clock

Is clock propagation stopped by the logic on the design, does a clock have reconvergent paths

Are clock crossings correctly constrained using false paths, clock groups

Do case analysis values conflict with each other

Do setup MCPs have accompanying hold MCPs, are there exceptions specified with a very broad scope, do exceptions overlap

Are input/output delays complete

Do constraints refer to objects that do not exist, or apply to objects that they should not, or are written

Are constraints written using best known methods, avoiding common pitfalls