FishTail’s formal constraint lint works off netlist or RTL input with the constraints specified in either SDC or TCL format. It has been applied to designs with more than 100M cell instances and with more than thousands of clocks.
Constraint Lint Verification Features
FishTail’s formal constraint lint solution allows engineers to get feedback on the following aspects of their SDC constraints:
Case Analysis
Verification
Clock Propagation
False Paths
Logically Exclusive
Clock Groups
What Makes us Different
FishTail’s formal constraint lint is not noisy. Subtle issues are reported. Formal technology is used to ensure that the warnings are legitimate and require review. Our primary focus is not on tool runtime but on reducing designer review and on reporting bugs that other tools do not catch. A powerful debug environment allows engineers to quickly rootcause issues.