FishTail’s SDC Promotion solution is used to propagate IP constraints up the design hierarchy and facilitates IP reuse by an SoC integration team.

SDC Promotion Features

Automatic mapping of SoC clocks to IP clocks

The tool propagates clocks defined at the SoC or in other IPs to automatically establish a mapping between clocks defined outside the IP and the clocks defined within the scope of the IP. This clock mapping is used to promote generated clocks, clock groups and exceptions that refer to clocks. The tool handles the situation where the number of clocks defined on the input port of an IP is not the same as the number of clocks that propagate to that port.

Maintaining scope of IP exceptions

The tool ensures that the scope of clock groups and exceptions is not changed when they are promoted up the design hierarchy. This is crucial to ensuring that an exception that is valid within the scope of an IP is correctly promoted.

Creation of top-level clock definitions when required

Engineers do not need to provide the tool with top-level clock definitions. If none are provided the tool creates top-level clocks based on the definition of IP clocks and flags situations where the clock definitions at the IP level are inconsistent with each other.

Verification of promoted SDC

Once IP constraints are promoted, the quality of the promotion is verified using FishTail’s block-at-top SDC Equivalence verification solution.

What Makes us Different

FishTail’s SDC promotion is fast, correct and used to easily refresh SoC constraints when a new revision of an IP needs to be integrated by an SoC team. Engineers are able to specify different SDCs for different instances of an IP. Engineers are able to use IP constraints to create an SoC constraint file when none exists. The promotion flow automatically verifies the quality of the generated SDC using SDC Equivalence verification.

SDC Management Solutions

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RTL Glitch Verification

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