SDC Promotion

The tool propagates clocks defined at the SoC or in other IPs to automatically establish a mapping between clocks defined outside the IP and the clocks defined within the scope of the IP. This clock mapping is used to promote generated clocks, clock groups and exceptions that refer to clocks. The tool handles the situation where the number of clocks defined on the input port of an IP is not the same as the number of clocks that propagate to that port.

The tool ensures that the scope of clock groups and exceptions is not changed when they are promoted up the design hierarchy. This is crucial to ensuring that an exception that is valid within the scope of an IP is correctly promoted.

Engineers do not need to provide the tool with top-level clock definitions. If none are provided the tool creates top-level clocks based on the definition of IP clocks and flags situations where the clock definitions at the IP level are inconsistent with each other.

Once IP constraints are promoted, the quality of the promotion is verified using FishTail’s block-at-top SDC Equivalence verification solution.