SDC Equivalence

SDC Equivalence is used to verify that the functional-mode synthesis constraints applied to the RTL constrain the design in the same way as the functional-mode signoff constraints applied to the signoff netlist. This allows teams to confirm the integrity of their RTL constraint signoff and guard against synthesis transformations that are not accompanied by matching constraint transformations.

SDC Equivalence allows engineers to ensure that IP constraints are correctly reused by an SoC, or SoC constraints are correctly pushed down to an implementation block. SDC Equivalence establishes if every path on a block needs to meet the same timing requirement when the block is timed standalone using the block-level constraints or when the block is timed in the context of an SoC using SoC constraints. SDC Equivalence allows engineers to catch mistakes in the way timing exceptions are rewritten when an IP is reused by an SoC, or discrepancies in the clock and I/O delay definitions used by an implementation block compared to the way the logic is timed by an SoC.

SDC Equivalence allows engineers to check if a merged-mode constraint file constrains a design the same way as its multi-mode constraints. This allows engineers to confirm that the merged-mode constraints used by implementation are equivalent to multi-mode constraints used for timing signoff.

SDC Equivalence allows engineers to confirm if a .lib model extracted from the netlist or RTL description of a design correctly captures the I/O timing of the design. Engineers can use SDC equivalence to identify bugs in the extracted .lib where not all the timing arcs are extracted, or a timing arc is extracted relative to the wrong clock edge, etc.