FishTail’s SDC Demotion solution is used to push top-level constraints down to implementation blocks.

SDC Demotion Features

Creation of boundary constraints for blocks from top-level constraints

The tool propagates top-level clocks to establish clock definitions at the input ports of a block. Input/Output delays for ports are created based on the registers that drive or are driven by these ports at the top-level and the manner in which these registers are clocked. Top-level constants are propagated to create case analyses on block-level input ports. Top-level timing exceptions are moved to the ports on a block when appropriate.

User control when a block is multiply instantiated

When a block is multiply instantiated by an SoC each instance of the block could be constrained differently. Engineers control whether they get a different SDC for each instance of the block, or a “union” SDC that accounts for all the different ways the block is constrained.

Verification of demoted SDC

Once top-level constraints are pushed down to blocks, the quality of the demotion is verified using FishTail’s block-at-top SDC Equivalence verification solution. This checks whether a block is constrained the same way standalone with its demoted SDC as it is constrained as part of the SoC.

What Makes us Different

FishTail’s SDC demotion is fast and accurate. Multiple instantiations of a block are handled and the demotion flow automatically verifies the quality of the generated SDC using SDC Equivalence verification.

SDC Management Solutions

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RTL Glitch Verification

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