FishTail’s Timing-Exception Generation capability identifies false and multi-cycle paths that result from the functionality of the design. We strongly recommend generating exceptions with RTL input. FishTail’s constraint mapping technology is used to map RTL exceptions to a gate-level netlist.
Timing Exception Generation Features
Multi-Cycle
Path Generation
False
Path Generation
What Makes us Different
FishTail generates a comprehensive and correct set of timing exceptions for a design. All exceptions are generated for formal reasons, not design rules, and the logical property that results in a timing exception can be extracted from the tool by generating SVA for each exception. The timing exceptions generated by the tool typically result in a 1-3 % improvement in area and power consumption and a much more dramatic reduction in the number of paths that don’t meet timing at the end of P&R. Engineers can generate all the exceptions for their design, or if they want, just the timing-critical exceptions.