FishTail’s Timing-Exception Generation capability identifies false and multi-cycle paths that result from the functionality of the design. We strongly recommend generating exceptions with RTL input. FishTail’s constraint mapping technology is used to map RTL exceptions to a gate-level netlist.

Timing Exception Generation Features

False-Path Generation

The tool generates a false-path when it finds that a transition on a startpoint can never propagate to an endpoint once the logic along the path is accounted for. The logic along both data and clock paths is considered when making this determination. Asynchronous clock crossings are ignored.

Multi-Cycle Path Generation

The tool generates a multi-cycle path when it finds that a transition on a startpoint cannot propagate to an endpoint in the same cycle. Both clock and datapath logic is accounted for. If the logic on a design allows for MCPs greater than 2 cycles the tool correctly computes the exact multi-cycle shift. When multiple clocks propagate to a start or endpoint the tool makes an MCP determination for each synchronous clock crossing.

Timing-Critical Exceptions

If engineers are only interested in timing exceptions that apply to the critical timing paths on a design they first run a FishTail utility in their implementation or STA tool. This utility extracts all endpoints with slack less than a user-specified critical value. The tool only generates exceptions for these endpoints and the generated exceptions are further filtered to confirm that they apply to timing-critical paths.

Compact Timing Exceptions

After having identified all the exceptions on a design, the tool examines the paths that these exceptions apply to, and establishes the most concise way of writing exceptions that apply to all of these paths. This reduces the number of exceptions that are imported into implementation or STA tools and ensures that the runtime of these tools is not adversely impacted by large numbers of timing exceptions.

Verification of Timing Exceptions

All exceptions generated by the tool are formally verified using FishTail’s SDC Verification solution. In addition, engineers can generate SVA for each exception and verify the SVA using RTL simulation.

Multi-Cycle
Path Generation

False
Path Generation

What Makes us Different

FishTail generates a comprehensive and correct set of timing exceptions for a design. All exceptions are generated for formal reasons, not design rules, and the logical property that results in a timing exception can be extracted from the tool by generating SVA for each exception. The timing exceptions generated by the tool typically result in a 1-3 % improvement in area and power consumption and a much more dramatic reduction in the number of paths that don’t meet timing at the end of P&R. Engineers can generate all the exceptions for their design, or if they want, just the timing-critical exceptions.

SDC Generation Solutions

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QoR Impact of Generated Timing Exceptions

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