FishTail’s Mode Generation capability takes the RTL/netlist description for a design along with its clock definitions and identifies the different modes on the design and the case analyses that puts the design into any given mode.
Mode
Generation
What Makes us Different
Our mode generation analyzes the clock muxes on a design and based on that creates a complete set of modes with the case analyses that put the design into each mode. The case analyses are created on input ports and mode-configuration registers.
