FishTail’s Mode Generation capability takes the RTL/netlist description for a design along with its clock definitions and identifies the different modes on the design and the case analyses that puts the design into any given mode.

Mode Generation Features

Complete set of modes identified

By using our mode generation capability engineers can ensure that their multi-mode constraints are complete and that they are not missing any modes that need to be timed.

Case analyses on input ports and registers

The case analyses generated by the tool is on input ports and mode-configuration registers, not on the select pins of clock muxes.


What Makes us Different

Our mode generation analyzes the clock muxes on a design and based on that creates a complete set of modes with the case analyses that put the design into each mode. The case analyses are created on input ports and mode-configuration registers.

SDC Generation Solutions