FishTail’s Lib Generation capability generates a .lib model from either RTL or netlist input. The input/output delays specified in the SDC constraints are used to establish the timing values for the extracted timing arcs.
Lib Generation Features
What Makes us Different
FishTail’s Lib Generation flow works with RTL input, unlike other tools that require netlist input. The timing values in the extracted lib model are not impacted by the current status of the block implementation. This allows the generated Lib model to be used for design budgeting as it captures the expected timing at the interface of a block should the implementation meet the timing requirements specified by the input/output delays. The tool has the ability to generate a multi-mode Lib model when provided multi-mode SDC as input.