FishTail’s Lib Generation capability generates a .lib model from either RTL or netlist input. The input/output delays specified in the SDC constraints are used to establish the timing values for the extracted timing arcs.

Lib Generation Features

SDC is optional

The tool can be used to extract a .lib model with just RTL input and without any SDC constraints. The expectation is that in this situation all the timing arcs will be extracted by the tool with the correct timing-sense and relative to the correct clock edge. If SDC constraints are provided then the input/output delays are used to establish timing-arc values. In this situation, it is assumed that the specified input/output delay is consumed by logic outside the block, and the remaining delay is the delay of the logic inside the block.

Multi-Mode Lib

Multi-Mode SDCs may be provided as input to the tool to generate a single multi-mode lib model. Engineers can use the set_mode command when the .lib model generated by FishTail is used and have just the timing arcs for that mode come into play.

Verification of Generated Lib

The lib model generated by the tool is verified using FishTail’s SDC Equivalence verification solution.

What Makes us Different

FishTail’s Lib Generation flow works with RTL input, unlike other tools that require netlist input. The timing values in the extracted lib model are not impacted by the current status of the block implementation. This allows the generated Lib model to be used for design budgeting as it captures the expected timing at the interface of a block should the implementation meet the timing requirements specified by the input/output delays. The tool has the ability to generate a multi-mode Lib model when provided multi-mode SDC as input.

SDC Generation Solutions

Clock Generation

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Mode Generation

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Clock-Group Generation

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Clock-Sense Generation

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Timing Exception Generation

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Lib Generation

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