FishTail’s Clock-Sense Generation capability creates set_clock_sense constraints when the propagation of a clock is completely stopped, or the propagation of a specific clock-sense is stopped. Clock-sense generation is also used to reduce the clocks-per-register on a design without impacting STA results. Clock-sense generation works off RTL or netlist input.
Clock-Sense Generation Features
Clock-Sense
Generation
Clock-Sense
Generation
What Makes us Different
By generating a complete set of clock-sense constraints for a design we reduce pessimism in STA. By reducing the clocks-per-register we allow implementation tools to run faster.