Clock-Sense Generation

FishTail’s Clock-Sense Generation capability creates set_clock_sense constraints when the propagation of a clock is completely stopped, or the propagation of a specific clock-sense is stopped. Clock-sense generation is also used to reduce the clocks-per-register on a design without impacting STA results. Clock-sense generation works off RTL or netlist input.

Clock-Sense Generation Features

Generation of Stop Propagation Clock Sense Constraints

When the clock gating and muxing logic on a design result in the propagation of a clock being stopped the tool generates a set_clock_sense –stop_propagation constraint.

Generation of Positive/Negative Clock Sense Constraints

When both senses of a clock propagate to the input of a gate, but only one sense is allowed to propagate further, the tool creates a set_clock_sense –positive or –negative constraint as required.

Reduction of Clocks/Register

A user can optionally ask the tool to create set_clock_sense –stop_propagation constraints to prevent the propagation of a clock beyond a pin on the clock network, if the further propagation of the clock has no impact on the STA results of the design. This reduces the clocks-per-register on a design, which in-turn improves the runtime of implementation and STA tools, without any impact on STA results.

Clock-Sense
Generation

What Makes us Different

By generating a complete set of clock-sense constraints for a design we reduce pessimism in STA. By reducing the clocks-per-register we allow implementation tools to run faster.

SDC Generation Solutions

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DAC User Track Presentation 2017

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Clock-Sense Generation