FishTail’s Clock-Group Generation capability identifies the exclusive relationship between clocks using either RTL or netlist input.
Clock-Group Generation Features
Logically
Exclusive Clock Group
Physically
Exclusive Clock Group
What Makes us Different
We create a complete and correct set of exclusive clock groups for a design regardless of the complexity of the clock-muxing logic on a design. These clock groups are immediately verified by the Formal Constraint Lint technology of our SDC verification solution.