FishTail’s Clock-Group Generation capability identifies the exclusive relationship between clocks using either RTL or netlist input.

Clock-Group Generation Features

Generation of Physically-Exclusive Clock Groups

When multiple clocks are defined on the same pin, or when two clocks cannot exist on the design at the same time, the tool creates physically-exclusive clock groups.

Generation of Logically-Exclusive Clock Groups

The tool automatically generates logically exclusive clock groups by analyzing the clock-muxing logic on a design. When two clocks are partially-exclusive (i.e. they time both exclusive and single-cycle paths) then the user can optionally ask the tool to insert divide-by 1 generated clocks at the output of clock muxes so that the exclusive relationship can be specified where it exists.

Generation of Asynchronous Clock Groups

Based on the asynchronous clock groups specified for the master clocks on a design by an engineer, the tool creates asynchronous clock groups for the generated clocks derived from these master clocks.

Logically
Exclusive Clock Group

Physically
Exclusive Clock Group

What Makes us Different

We create a complete and correct set of exclusive clock groups for a design regardless of the complexity of the clock-muxing logic on a design. These clock groups are immediately verified by the Formal Constraint Lint technology of our SDC verification solution.

SDC Generation Solutions