FishTail’s Clock Generation capability automates the creation of the clock and generated-clock definitions for a design. Both netlist and RTL is supported. Engineers can optionally provide the tool any existing constraints for the design, and have the tool generate what is missing.
Clock
Generation
What Makes us Different
We create all the clock definitions for a design without generating any unnecessary constraints. Engineers can use our clock browser to understand the motivation for the constraints we generate and the clocking structure of the design. Clock names, periods and I/O delay budgets can be manipulated in Excel. All the constraints generated by the tool are verified to confirm that they are complete and correct.