Clock Generation

Our clock generation solution understands clock muxing and gating logic and only creates clocks and generated clocks at the pins or ports where clocks should be stamped.

We create all the clocks and generated clocks required for a design. Our focus is not merely on ensuring that every register on a design is clocked, but on ensuring that it is clocked by all the clocks required. We specify the master clock associated with each generated clock and create as many generated clocks as master clocks that propagate to the clock pin of a clock divider.

Engineers can optionally ask the tool to create I/O delays for a design based on the clocking of the registers that drive or are driven by a port. The tool creates max-delay constraints for feedthrough paths between ports.

The clock and input/output delay constraints generated by the tool can be viewed and manipulated in Excel. We have a utility that converts SDC to Excel and then Excel back to SDC.

We provide an intuitive GUI to visualize the clock network on a design. This helps designers familiarize themselves with the clock network for an IP they are not familiar with.

Immediately after the clock constraints are generated by the tool we deploy the Formal Constraint Lint technology of our SDC verification solution to ensure that there is no issue with the generated constraints and to confirm that they are indeed complete and correct.