FishTail’s Clock Generation capability automates the creation of the clock and generated-clock definitions for a design. Both netlist and RTL is supported. Engineers can optionally provide the tool  any existing constraints for the design, and have the tool generate what is missing.

Clock Generation Features

No unnecessary clock definitions

Our clock generation solution understands clock muxing and gating logic and only creates clocks and generated clocks at the pins or ports where clocks should be stamped.

Complete clock definitions

We create all the clocks and generated clocks required for a design. Our focus is not merely on ensuring that every register on a design is clocked, but on ensuring that it is clocked by all the clocks required. We specify the master clock associated with each generated clock and create as many generated clocks as master clocks that propagate to the clock pin of a clock divider.

Creation of I/O Delays

Engineers can optionally ask the tool to create I/O delays for a design based on the clocking of the registers that drive or are driven by a port. The tool creates max-delay constraints for feedthrough paths between ports.

Excel integration

The clock and input/output delay constraints generated by the tool can be viewed and manipulated in Excel. We have a utility that converts SDC to Excel and then Excel back to SDC.

Clock browser

We provide an intuitive GUI to visualize the clock network on a design. This helps designers familiarize themselves with the clock network for an IP they are not familiar with.

Verification of generated constraints

Immediately after the clock constraints are generated by the tool we deploy the Formal Constraint Lint technology of our SDC verification solution to ensure that there is no issue with the generated constraints and to confirm that they are indeed complete and correct.


What Makes us Different

We create all the clock definitions for a design without generating any unnecessary constraints. Engineers can use our clock browser to understand the motivation for the constraints we generate and the clocking structure of the design. Clock names, periods and I/O delay budgets can be manipulated in Excel. All the constraints generated by the tool are verified to confirm that they are complete and correct.

SDC Generation Solutions

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Clock Browser