Value Proposition

By automatically generating correct-by-construction constraints from the RTL for a design we shorten the time and effort required to perform this task. We ensure consistency in how constraints are written by geographically dispersed teams with varying levels of SDC expertise.

Our best-in-class exception generation identifies exclusive clock groups, false and multi-cycle paths based on the functionality of a design. These exceptions to single-cycle timing typically provide a 1-3% reduction in area and power consumption. They almost always provide a dramatic reduction in the number of paths that do not meet timing at the end of P&R.

We are able to significantly improve P&R runtimes by generating clock-sense stop-propagation constraints that reduce the clocks/register on a design without impacting QoR or changing timing results.

As part of the SDC generation flow we automatically run SDC verification to critique the quality of the generated constraints. We allow engineers to generate assertions for the timing exceptions extracted by the tool, allowing these exceptions to be verified using third-party simulation tools.

FishTail’s SDC generation solution reads the RTL for a design, and from just that information, we generate the clock definitions, input-output delays, clock groups, clock senses and timing exceptions for the design. Optionally, the tool can also be asked to identify the modes on the design and the case analyses that put the design into a specific mode. We also generate .lib models from RTL and these models are used for design budgeting while the implementation of a block is still in progress. The constraints generated by the tool are verified using our SDC verification solution.

SDC Generation Solutions

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Constraint Generation

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Constraint Generation

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Constraint Generation

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