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Products

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Lite

For the generation of clocks and .lib models, structural analysis of constraints during mode-merging and equivalence checking, and interactive debug of verification results

Focus

For the generation of clocks, clock groups, clock senses, timing exceptions, and .lib models

Confirm

For formal constraint lint, the verification of generated clocks, timing exceptions, glitches, reset-domain crossing, interactive debug of verification results

Refocus

For checking constraint syntax, mapping constraints from one design representation to another, the promotion and demotion of constraints and for SDC equivalence verification

Turbo

For parallelizing the execution of Focus and Confirm on SoCs

  • Product Configuration

  • 1. Tell us about your design

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  • 2. Tell us about your problem

  • 3. Tell us about the task:

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    Lite

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    Focus

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    Confirm

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    Refocus

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    Turbo

FishTail Design Automation provides breakthrough technology for improving chip design by verifying, generating and managing SDC constraints without any noise.

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