Lite

For the generation of clocks and .lib models, structural analysis of constraints during mode-merging and equivalence checking, and interactive debug of verification results

Focus

For the generation of clocks, clock groups, clock senses, timing exceptions, and .lib models

Confirm

For formal constraint lint, the verification of generated clocks, timing exceptions, glitches, reset-domain crossing, interactive debug of verification results

Refocus

For checking constraint syntax, mapping constraints from one design representation to another, the promotion and demotion of constraints and for SDC equivalence verification

Turbo

For parallelizing the execution of Focus and Confirm on SoCs