logo
logo
  • Verification
    • Formal Constraint Lint
    • Generated Clock Verification
    • Timing Exception Verification
    • Glitch Verification
    • RDC Verification
    • CDC Verification
  • Management
    • SDC Mapping
    • SDC Promotion
    • SDC Demotion
    • Mode Merging
    • SDC Equivalence
  • Generation
    • Clock Generation
    • Mode Generation
    • Clock-Sense Generation
    • Clock-Group Generation
    • Timing Exception Generation
    • Lib Generation
  • Products
  • Resources
    • White Papers
    • Presentations
    • Demos
  • About
    • News
    • Careers
    • Contact

Partners

FishTail Design Automation provides breakthrough technology for improving chip design by verifying, generating and managing SDC constraints without any noise.

© 2022 Synopsys, Inc. All Rights Reserved.

Contact us

Address: 690 East Middlefield Rd
Mountain View, CA 94043

Phone: 800-541-7737

Email: info@fishtail-da.com

Useful Links

Verification

Generation

Management

Privacy Policy

Products

Resources

About

Copyright ©2018 FishTail Design Automation, All rights reserved

Privacy Preference Center

Privacy Preferences

 
 

Please enter your information and an email with your requested resource will be sent to your inbox.