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  • Verification
    • Formal Constraint Lint
    • Generated Clock Verification
    • Timing Exception Verification
    • Glitch Verification
    • RDC Verification
    • CDC Verification
  • Management
    • SDC Mapping
    • SDC Promotion
    • SDC Demotion
    • Mode Merging
    • SDC Equivalence
  • Generation
    • Clock Generation
    • Mode Generation
    • Clock-Sense Generation
    • Clock-Group Generation
    • Timing Exception Generation
    • Lib Generation
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    • White Papers
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    • What’s in a Name

FishTail Design Automation provides breakthrough technology for improving chip design by verifying, generating and managing SDC constraints without any noise.

Contact us

Address: 5285 Meadows Rd., Suite 275
Lake Oswego, OR 97035

Phone: (503) 598-2210

Email: info@fishtail-da.com

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